1. Field of the Invention
The invention relates to electronic devices, and more particularly, to a converter with an additional DC offset and method thereof.
2. Description of the Related Art
An offset of a normal electric signal often causes many problems. For example, in audio applications, a DC offset of output from an audio circuit causes pop-noise to human ears. Currently, the method to resolve such a pop-noise problem is to add a single inverted DC offset to reduce the DC offset but there are limitations on processing and environmental variations.
The above method can be applied to analog-to-digital converters (ADC) and digital-to-analog converters (DAC) but elimination of the DC offset or pop-noise is restricted. As shown in FIG. 1A, ADC 100a utilizes switch-cap. ADC 100a includes a loop filter 100a1, an N-bit quantizer 100a2 and an N-bit internal DAC 100a3. The above method can be applied to DAC 100b shown in FIG. 1B utilizing switch-cap. DAC 100b includes an operational amplifier 100b1, paired-up capacitors C1, C2 and paired-up switches S1, S2, S3, S4.
A 3-bit sigma-delta DAC is used as an example. Please refer to FIGS. 1B and 2A. As shown in FIG. 2A, the capacitor C1 of DAC 100b includes 7 capacitor cells (capacitor cells 1˜7). A positive reference voltage VRP or a negative reference voltage VRN is supplied to the capacitor cells 1˜7 according to 3-bit input codes having values, 000, 001, 010, 011, 100, 101, 110, and 111, so as to generate eight different corresponding states. When DAC 100b switches to switches S1, S2, S3, S4 according to clock signals CK1 and CK2, DAC 100b generates eight different charges according to eight values of the digital codes:
(+1 +1 +1 +1 +1 +1 +1)*(C1/C2)=>+7*(C1/C2)
(+1 +1 +1 +1 +1 +1 −1)*(C1/C2)=>+5*(C1/C2)
(+1 +1 +1 +1 +1 −1 −1)*(C1/C2)=>+3*(C1/C2)
(+1 +1 +1 +1 −1 −1 −1)*(C1/C2)=>+1*(C1/C2)
(+1 +1 +1 −1 −1 −1 −1)*(C1/C2)=>−1*(C1/C2)
(+1 +1 −1 −1 −1 −1 −1)*(C1/C2)=>−3*(C1/C2)
(+1 −1 −1 −1 −1 −1 −1)*(C1/C2)=>−5*(C1/C2)
(−1 −1 −1 −1 −1 −1)*(C1/C2)=>−7*(C1/C2)
The charge ((+1 +1 +1 −1 −1 −1 −1)*(C1/C2)=>−1*(C1/C2)) is used as an example. It is assumed that the positive reference voltage VRP is +1V and the negative reference voltage VRN is −1V. Then, according to the input code 100, the charge −1*(C1/C2) is inputted to have capacitor cells 7, 6 and 5 receive the positive reference voltage VRP to obtain the value +1 (shown by blank rectangles) and to have capacitor cells 4, 3, 2 and 1 receive the negative reference voltage VRN obtain the value −1 (shown by rectangles with diagonal stripes). Therefore, the charge is (+1+1+1−1−1−1−1)*(C1/C2)=−1*(C1/C2). If C1=C2, the charge is equal to −1. The charge obtained from the other input code can be derived by analogy. Thus, the operational amplifier 100b1 generates a DC bias or Von having the charges +7, +5, +3, +1, −1, −3, −5, −7.
However, generally capacitors of a DAC or ADC may have capacitor mismatch due to processing drift, environmental variations or asymmetrical factors so as to cause a DC offset of the DC bias Vop or Von. As shown in FIG. 2B, it is assumed that the capacitor cell 7 has capacitor mismatch with the other capacitor cells 1˜6. As shown in the figure, the actual capacitance of the capacitor cell 7 is shown by the solid-line frame while the dashed-line frame of the capacitor cell 7 shows the capacitance matching with that of the other capacitor cells. According to the prior art, at the time, in order to compensate the capacitance deficiency of the capacitor cell 7 (area difference between the solid-line frame and the dashed-line frame), a tiny single inverted DC offset is generated to eliminate the DC offset caused by capacitor mismatch of the capacitor cell 7. However, due to processing drift, it is difficult to predict and produce the tiny capacitance (or variation of capacitor cells). Therefore, the DC offset problem of DAC and ADC still cannot be solved based on the previous mentioned technique.